The present invention relates to the formation of alignment marks for photolithographic masks in semiconductor wafer fabrication. More particularly, the present invention relates to alignment marks formed by physical vapor deposition shadowing during deposition of tungsten in alignment mark mold trenches of certain shapes.
Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits (ICs) in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with others such as doping, and heat treatments. Layering is an operation used to add thin layers of material (typically insulator, semi-conductor or conductor) to the surface of the semiconductor wafer. Layers are typically either grown (for example, thermal oxidation of silicon to grow a silicon dioxide dielectric layer) or deposited by a variety of techniques such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), including evaporation and sputtering. Patterning, is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
The objective of the photolithographic process is to create in or on the wafer surface the various parts of a device or circuit in the exact dimensions specified by the circuit design ("resolution"), and to locate them in their proper location on the wafer surface ("alignment"). In order for the finished circuit to function properly, the entire circuit pattern circuit must be correctly placed on the wafer surface, and the individual parts of the circuit must be in the correct positions relative to each other. Since the final wafer pattern is generated from several photomasks applied to the wafer sequentially, misalignment of even a single mask layer can cause the entire circuit to fail.
In order to provide proper alignment of mask layers, photolithography tools are equipped to locate certain alignment marks on preceding layers. The alignment of two features on successive layers is straight forward. However, when, as is frequently the case, two features on non-successive layers require alignment, the location of the alignment marks through an intervening layer is more complicated. In many instances during fabrication, the preceding layer is transparent or translucent, allowing alignment marks on an underlying wafer to be optically detected by techniques well known in the art, such as bright field or dark field alignment. For example, a metal layer is typically covered by an oxide dielectric layer. A photolithography stepper using bright field alignment will be able to locate the metal lines in the metal layer, to which contact holes must be aligned, through the transparent oxide layer. The stepper may then properly align the mask for the via holes.
However, in some cases alignment of non-successive layers in which the intervening layer is opaque is required. This is the case with metal layer alignment, where it may be necessary to align a mask to a mark on a layer that is covered with an opaque metal layer. Alignment in such cases has been achieved by providing some topography in, for example, the underlying the metal layer. An example of this technique is illustrated in FIGS. 1A through 1D.
FIG. 1A shows a cross-section of a portion of a semiconductor wafer 101 during fabrication having a trench 100 etched in a surface layer 102 to provide a mold for an alignment mark. The alignment mark trench is typically adjacent to a die on the semiconductor wafer, and each die typically has several alignment marks associated with it. In a preferred embodiment, the surface layer 102 is a dielectric layer, such as an oxide, nitride, polymer, or composite of these, and will generally be referred to as such in this application.
The mark is typically formed by deposition of tungsten 104 by CVD in the mold trench 100. Conventional tungsten deposition is typically preceded by deposition of a thin layer of PVD or CVD titanium nitride (TiN) as a glue layer (not shown) for the subsequently deposited tungsten. The deposition typically has two phases. First a relatively thin nucleation layer 103 of tungsten with fine grain size and conformity having an equiaxed grain structure is deposited over the surface layer 102. This nucleation layer 103 provides a good base on the substrate material for subsequent bulk deposition of tungsten. The bulk tungsten 105, which is typically used to form the main body of the alignment mark due to its high deposition rate, has a columnar structure with uneven grain size and distribution and variable defect density relative to the nucleation layer 103. Since the CVD tungsten is conformal, a deposition trench 106, which follows the contours of the mold trench 100, remains in the surface of the wafer 108 following tungsten deposition. This deposition trench 106 ultimately serves as an alignment mark.
FIG. 1B shows the same wafer portion cross-section as in FIG. 1A following planarization of the wafer surface 108 according to an etch back technique well known in the art. The tungsten layer 104 above the level of the dielectric 102 has been removed, and the deposition trench 106 in the wafer surface is maintained by removal of tungsten in the mold trench 100 by the etch back. FIG. 1C shows the portion of the wafer 101 following deposition of a metal layer 110, typically AlCu, by PVD. PVD deposition is directional rather than conformal, however it does deposit the metal layer 110 in a predictable manner in the absence of obstructions so that the topographical pattern produced by the deposition trench 106 is reproducible.
As shown in FIG. 1D, metal deposition is followed by application of a conformal photoresist layer 112 which is subsequently patterned for the next layer (not shown). The result of this process is that the deposition trench 106 is maintained in a reproducible manner, providing a reliable alignment mark for the stepper when patterning the photoresist layer 112. The alignment mark is detectable, due to the topography it produces in the wafer surface, and provides detection accuracy, since the intervening process steps maintain the topography in a reproducible manner.
While the adoption of chemical mechanical polishing (CMP) of wafer surfaces during fabrication produced improved planarization results over etch back techniques, it has presented further problems for mask alignment. For example, as illustrated in FIG. 2A, a trench 200 is etched in a dielectric layer 202 at the surface of a wafer 204 to serve as a mold for an alignment mark. A tungsten layer 206 is conformally deposited over the wafer surface 208 by CVD. As described above, a conventional tungsten layer is composed of a thin nucleation layer 205 deposited over the dielectric 202, and bulk tungsten layer 207 over the nucleation layer 205. The CVD tungsten is conformal and forms a deposition trench 210 following the contours of the mold trench 200, with the bulk tungsten forming the walls 212 of the deposition trench.
As illustrated in FIG. 2B, as the wafer surface 208 is planarized by CMP, slurry (not shown) accumulates in the deposition trench 210. Since the polishing pad (not shown) does not contact the deposition trench walls 212 to polish them or remove the slurry, the walls 212 of the trench 210 are attacked by the oxidizing slurry. Due to the irregular structure of the bulk tungsten, discussed above, from which they are formed, the walls 212 are rendered uneven in an unpredictable way by the CMP slurry attack. As a result, the profile of the deposition trench 210 following CMP may be asymmetric and non-reproducible, as shown in FIG. 2B. This, in turn, results in an asymmetric and non-reproducible topography in the wafer surface 208 following metal deposition of the metal layer 214 and photoresist 216, illustrated in FIGS. 2C and 2D, respectively. Therefore, while the deposition trench alignment mark 210 may be detectable due to its topography, its detection accuracy is unreliable due to its unpredictable deformation by the CMP slurry.
Accordingly, what is needed are methods and compositions for obtaining consistent alignment mark profiles with both detectability and detection accuracy for use in conjunction with CMP processes during semiconductor fabrication.